1. Field of the Invention
The present invention relates to a parallel data output control circuit that outputs data for D/A conversion to a DAC (D/A converter), and also controls a DA output cycle.
2. Description of the Background Art
Conventionally, a parallel data output control, in which data for D/A control is outputted to a DAC and a DA output cycle is controlled, has typically been performed by means of an interruption command from a timer made by software processing executed by a prescribed CPU (MCU) built in a microcomputer or the like. As a technique in which data is transmitted by the microcomputer (CPU) in controlling an object to be processed such as the above-mentioned DAC, there is, for example, a serial transmission/reception circuit disclosed in Japanese Patent Application Laid-Open No. 2001-77800.
As thus described, since the parallel data output control has conventionally been executed by means of the interruption command made by the software processing, there has been a problem in that a timing at which the DAC itself captures data for D/A conversion largely depends upon a processing statues of the CPU which executes the software processing.
FIGS. 11A and 11B and FIGS. 12A and 12B show explanatory views for explaining the above-mentioned conventional problem. As shown in FIG. 11A, modulation periods TM11 to TM13 are continuously executed at normal time when the software processing is executed without delay. It is to be noted that the modulation period means a period that is classified based upon contents of parallel data controls that define a later-described a DAC output voltage waveform, such as a DA conversion cycle.
On the other hand, as shown in FIG. 11B, at abnormal time when a blank period TB1 and a blank period TB2 are generated respectively between the modulation periods TM11 and TM12 and the modulation periods TM12 and TM13, a data transmission control is performed in which an update cycle for the data for D/A conversion outputted to the DAC is displaced as a whole.
FIGS. 12A and 12B are an explanatory view showing output voltage waveforms of the DAC at the normal time and the abnormal time. As shown in FIG. 12A, at the normal time, since the modulation periods TM11 to TM13 are continuously set, it is possible to obtain a desired DAC output voltage waveform.
On the other hand, as shown in FIG. 12B, at the abnormal time, the blank period TB1 and the blank period TB2 are generated among the modulation periods TM11 to TM13. Thereby, due to the generation of the blank periods TB1 and TB2, the desired DAC output voltage waveform is extended and formed into an undesired shape, as compared with FIG. 12A. As thus described, there has been a problem in that at the abnormal time, establishment of highly reliable communication is difficult and the desired DAC output voltage waveform cannot be generated.
There has also been a problem of a cost increase due to an increase in number of components out of the need for mounting another CPU to prevent an influence from another control and perform a target control in order to ensure reliability.